Understanding your UUT is the key to the design for an ITA. The more test points that can be tested simultaneously, the higher the probability of detecting an intermittent fault. Also the more test points that can be accessed and discretely connected to the IFD™ TE, the more flexible the testing paths, and subsequently the more defined the tests that can be performed on the UUT.
Inspecting the UUT for potential issues surrounding the 3Cs (Cable, Connectors and Chassis – this is where the majority of intermittence is found) is the first stage of the design of the ITA. Looking for possible mechanical failures and possible degradation due to corrosion, fatigue or stress are likely areas of intermittent faults. Clearly testing as many test points as possible helps to reduce the need for judgment on what and what not to test, but there is certainly a trade off. Therefore, identifying highly probable causes and testing these areas first could prove to be more cost effective.
A combination of the methods might be employed for an ITA, and this will be based on the UUT, the circuit types within the UUT, the possible fault mechanisms and the need to isolate a specific fault, the test point count and the test point available; there may have to be a compromise in the methods used to meet the testing requirements. Deciding how the UUT's test points will be connected to the IDFIS™ Virginia Panel or the VIFD™ J-connectors is an important step; here are some detailed points to consider:
Ø Careful consideration of how the ITA interfaces the tests points with the UUT is key to finding intermittent faults. The connections to the UUT, need to be as representative as possible, and mimic the methods employed by the system in which the UUT is used. Every effort to use mating connectors of the same type and make, manufactured PCB to represent sub-assemblies to mate with edge connectors, correct eyelets for terminal blocks, and pins of the same grade should be used where practicable.
Ø Where practicable, endeavour to orientate the ITA mated to the UUT in the same manner to which the UUT would be used. For example, a ITA to test a harness, it will be useful to orientate the harness in the same way as it would be in use, for example a harness on an undercarriage leg, or harness on an engine etc.
Ø An interconnection within the UUT with two or more connections is called a node and these can be identified from the UUT wiring diagram. Each of these connections or potential test points on this node should be designated the same nodal value within the test plan. Each node must have a nodal ground, either provided by a common ground as illustrated in IFD-Beta Method, or using a discrete nodal ground which is switch to ground by the IFD™ TE, as illustrated in IFD-Alpha Method; a blend of these modes may be appropriate for different circuits within the UUT and/or depending on the test point count vs test points available on the IFD™ TE.
Ø Every circuit or node needs to have a designated 'nodal ground' (or as they are also known 'test-ground').
Ø Try and keep 'nodal grounds' apart; the greater the separation the better ie spread them over different rows\connectors or J-connectors, or block\columns on Virginia Panels, especially nodes that have a large count of associated test points. Specifically don't have all the nodal grounds on one row or column. This helps to reduce cross-talk on the neural-network.
Ø Try and avoid using Test Point 1 as a nodal ground as this may affect Intermittence Testing in some edge cases.
Ø For nodes with a large test point count, try and allocate at least 1 extra nodal ground per 10-15 test points.
Ø It is a good idea to split the J-connectors or sub-parts of the Virginia Panel into logical batches of test points so that a specific part of the UUT can be tested in isolation to another part of the UUT. This is called families of connectors and allows the test system to be flexible in testing sub-parts of the UUT. For example on a dual-channel system, Channel-A might be placed on J1 & J2 and Channel-B on J3 & J4, thus allowing one channel to connected and tested on its own, if required.
Ø There is no requirement to use every test point on each J-connector or Virginia Panel block\column sequentially because this might make the ITA more complex than it needs to be.
Ø If a particular interface connector seems to be common, it might be a good idea to make a full interface connection for all the pins, even if they are not used on the current UUT; this ITA (or sub-ITA) could then make future testing of other UUT with the same connector quicker and more cost effective.
Ø Ensuring ITA connectors are the correct mating connector to mate with the UUT and not the actual connector on the UUT!
Ø Electrical isolation of the UUT to the other potential differences in the system is paramount; this is especially so for a UUT under test in an environmental chamber and shaker.
Ø Consider the routing of the ITA away from electrical and magnetic sources, especially for IDFIS™ the environmental shaker itself.
Ø For a Test Plan that may include the use of SSTDR, use a comparable cable type in the ITA (ie the same VOP) as the cable under test. Also use adjacent pairs of test points in the IFD™ TE, and route the cable in a uniform manner in the ITA. This will provide the best results for distance to state for SSTDR.
Ø Minimise the number of joins in the ITA and ensure joining methods are robust.
Ø Probes as Test Points: Once an intermittent event has been detected by the IFD™ TE, it may be necessary depending on methodology of the ITA design, to have spare test points available to help with fault isolation. Consider having one set of free or unassigned test points available for generic use at the UUT. It is recommend that this pair of test points are designated as 'Probes' in NODES™; they can be ran independently to the main ITA, and be either inside the environmental chamber for IDFIS™ or on the bench for VIFD™ ready for use as two banana jacks or similar for ad-hoc use via alligator clips or similar connection methods.
Ø Note that any test point not used on the IFD™ TE has to be made a BLANK in NODES™ by checking the Skip Test Point box in the
Test Point Add/Edit form, except BLANK test points that exist after the last designated test point.
Ø For some testing regimes, it might be advisable to BLANK any test points not used in the last row used of the J-connector ie if a UUT only had 14 test points, then test points 15 & 16 would be BLANK.
